In a floating gate memory, the information is stored by changing the quantity of charge on the floating gate of the memory transistor by means of one or more high voltages, with the result that the memory transistor conducts or blocks current under specific conditions. During the read-out of the cell, the control gates of all the memory transistors that are not to be read are held at a low potential (e.g., 0 volts), while the control gate of the cell to be read is brought to a higher read potential (e.g., 1.8 volts). A problem in the art is that memory transistors with a positive potential on the floating gate on the same signal line as the memory transistor to be evaluated can also contribute to a read current with a low control gate voltage and, thus, corrupt the read result for the memory cell to be read.
To date, the problem has been solved in that, in cells which are intended to have a conducting information state, the floating gate potential has been set so low that no current flows through them in the non-selected state. A disadvantage of this solution is that the high voltage has to be applied in pulsed fashion, and measured after each pulse to determine whether the cell has already reached the correct floating gate potential. Moreover, for the case where an excessively high floating gate potential is inadvertently reached, it is necessary to provide a recovery mechanism. In addition, the low floating gate potential in the cells reduces the read current and thus the read speed and restricts the read window.
In particular, there is a need for a floating gate memory in which these problems are avoided. The present invention satisfies these and other needs, as set forth in the following description.